ID:18266 Signal "<src>" drives multiple clock buffers.

CAUSE: The specified signal drives more than one clock buffer. This can affect skew balance across the signal's clock buffer nets. The software may automatically instantiate additional clock buffers at a node if existing buffers in the design are unable to drive required destinations (for example, this may happen if a dynamic switch clock is used or the clock is gated, but the source signal also drives to other non-gated destinations).

ACTION: Verify that the connectivity in the design is expected and that a single clock buffer net would be be incompatible with the design intent. Otherwise, modify the design to allow the use of a single clock buffer at the specified node.