ID:18976 The following <number_of_clocks> global signals have long path lengths from source to clock tree. A long path may limit performance of high-speed signals. Consider revising the clock pin location or use Clock Region and/or Logic Lock Region assignments to constrain the placement of the fan-out closer to the source

CAUSE: The path length from Clock Source to Clock Tree is long.

ACTION: Revise the clock pin location, or use Clock Region and/or Logic Lock Region assignments to constrain the placement of the fanout closer to the source.