ID:177009 The PLL(s) placed in location <name> have a compensation path specified that differs from the output clock network type driven by the PLL - the PLL will compensate for the output clocks

CAUSE: The following PLLs are set to be compensated with a clock network, but its compensated clocks are feeding both the global and regional clock networks. The PLL will compensate for output clocks.

ACTION: Use the Global Signal option assignments to set a common clock network type for the compensated clock signals, or use the Match PLL Compensation option assignment to choose a PLL output clock to compensate.