ID:204027 Generated simulation netlist will be non-hierarchical because the design has Signal Tap partitions, termination control logic and/or a design partition that contains bidirectional ports

CAUSE: You specified a simulation tool for the current project, and then either compiled the project or ran the EDA Netlist Writer. However, the generated simulation netlist is non-hierarchical because the design has Signal Tap partitions, termination control logic and/or a design partition that contains bidirectional ports.

ACTION: No action is required.