ID:10672 The following parameters' default values are not included in the symbol/instantiation/component file created.

CAUSE: You tried to create a symbol/instantiation/component file for a Verilog Design File (.v) or a VHDL Design File (.vhd). However, the design contains some parameters whose default values are not literals, and the default values are not included in the symbol/instantiation/component file generated. A literal is a constant value, such as a number or a string.

ACTION: No action is required.