ID:10872 Using initial value '<character>' for net "<string>" at <location>

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you declared an object that is represented by the specified net. However, you did not update the value of the net in your design. To match the simulated behavior of your design as closely as possible, Quartus Prime Integrated Synthesis has assigned the net to its initial value. Integrated Synthesis derives initial values differently depending on the source language:

• In Verilog HDL, Integrated Synthesis derives initial values from initial constructs, variable declaration assignments, and the net types tri1 and tri0.
• In VHDL, Integrated Synthesis derives initial values from the net's corresponding declaration. If the declaration has an explicit default or initial value, Integrated Synthesis honors the explicit default. Otherwise, it derives an implicit default value based on the signal or variable's type.

The following Verilog fragment declares a single-bit wire foo that is referenced but not assigned a value. Quartus Prime Integrated Synthesis will tie foo to 1, the initial value specified by its declaration.

reg foo = 1'b1;
wire o;
 
               
assign o = foo;

The following VHDL fragment declares two signals: data and foo. Signal foo consists of two bits, but only foo(1) has an actual value assignment. However, foo was declared with a default value. As a result, Quartus Prime Integrated Synthesis will tie foo(0) to 1, its default value.

signal data : std_logic;                           -- no default value 
signal foo : std_logic_vector(1 downto 0) := "01"; -- default value

               
foo(1) <= data;

In contrast, signal data (a scalar) has no assignment and no explicitly declared default value. Quartus Prime Integrated Synthesis will tie the net representing data to an implicit default value based on the signal's type. The implicit default value for a signal with scalar type T is T'LEFT, or the left-most value in the range of T. For example, the implicit default value for a signal with type STD_LOGIC is U, which Quartus Prime Integrated Synthesis models as X, a Don't Care value. (NOTE: Quartus Prime Integrated Synthesis does not generally treat X as a Don't Care during VHDL synthesis). Using implicit default values is highly discouraged because they may result in unintended or unpredictable design optimizations.