ID:10035 Verilog HDL or VHDL information at <location>: object "<name>" declared but not used

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you declared the specified object, but you never used the specified object in the design.

ACTION: If you intentionally didn't use the object, then no action is required, although you may remove the declaration in order to prevent this message in the future. If you intended to use the object, check the design for mistakes.