ID:10266 Verilog HDL Module Instantiation information at <location>: instance "<name>" connects port <number> to an empty expression

CAUSE: In a Verilog Design File (.v), you instantiated a module and left the specified port position unconnected by associating it with an empty expression in the Ordered Port Connect List. For example, the following Verilog HDL code instantiates module my_module and associates the second and third module ports with empty expressions, thereby leaving them unconnected:

wire a;

               
my_module inst(o, , );