ID:10041 Inferred latch for "<name>" at <location>

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you declared the specified net. You then assigned values to this net in a way that forces the net to hold its current value under certain conditions. As a result, Quartus Prime Integrated Synthesis inferred a latch for the specified net.

ACTION: No action is required.