ID:13843 VHDL information at <location>: object "<name>" is never assigned

CAUSE: In a VHDL Design File (.vhd) at the specified location, you specified an object that is either a variable in a process or an item in an array. However, the design never assigns a value to the object; that is, the design never uses the object on the left-hand side (LHS) of an expression. If the object is not used at a later stage in the design process (for example, when stitching different parts of the design together), the object is synthesized as a constant net.

ACTION: If you want the object to be synthesized as a constant net, no action is required. Otherwise, make sure the object is used at a later stage in the design process, or remove the object.