ID:13506 Verilog HDL Module Instantiation information at <location>: instance "<name>" connects port "<name>" to an empty expression

CAUSE: In a Verilog Design File (.v), you instantiated a module and left the specified port unconnected by associating it with an empty expression in the Port Connect List for the instance. For example, the following Verilog code instantiates module my_module. and associates port aux1 and aux2 with empty expressions, thereby leaving them unconnected:

wire a, b, o;

               
my_module inst(.a(a), .b(b), .o(o), .aux1(), .aux2());