ID:13522 Verilog HDL Declaration information at <location>: object "<name>" differs only in case from object "<name>" in the same scope

CAUSE: In a Verilog Design File (.v), you declared an object with the specified name, which differs only in case from the name of an object previously declared in the same scope. Although Verilog is a case-sensitive language, declaring objects with names that differ only in case can cause confusion.

ACTION: No action is required. To eliminate this message, rename one of the objects.