ID:332097 The following timing edges are non-unate. The Timing Analyzer will assume pos-unate behavior for these edges in the clock network.

CAUSE: A non-unate timing edge was found in the clock network; this edge will be treated as a pos-unate edge. This behavior can be the result of gated logic such as an XOR, select path of a MUX, etc.

ACTION: No action may be necessary. If applicable, the non-unate logic elements in this clock path can be changed to those known to exhibit a pos-unate or neg-unate behavior. Alternatively, a generated clock can be created on the output of the logic element to explicitly specify the desired waveform.