ID:17051 WYSIWYG Clock Delay Control primitive <name> converted to a wire

CAUSE: The specified WYSIWYG Clock Delay Control primitive was intended for a different device family and was converted to a wire with minimum delay.

ACTION: If this conversion is acceptable, no action is required. If this conversion is not acceptable, and if you are using an EDA tool, contact the technical support for the EDA tool regarding this message. If the specified WYSIWYG was used to implement a double data rate memory interface, Intel strongly recommends the use of the ALTMEMPHY Megafunction to implement the interface.