ID:11951 Module instance "<serdes_inst>", which is a <serdes_wys_type> primitive and belongs to an ALTLVDS interface, should have a bus width of exactly <word_width> connected to <parallel_data_port> port.

CAUSE: The serialization/deserialization (SERDES) DPA should have a port of width which is equal to the parallel data width connected to this port.

ACTION: Ensure the appropriate number of connections are made during the ALTLVDS megafunction generation.