ID:276018 RAM logic "<name>" is uninferred due to inconsistent secondary signals in write logic

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because the registers in the write logic for the RAM do not all use the same secondary signals.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, ensure that the write logic registers all use the same secondary signals.