ID:276006 RAM logic "<name>" is uninferred due to "logic" being set as ramstyle synthesis attribute

CAUSE: You specified a set of registers in a Verilog Design File (.v) or VHDL Design File (.vhd) that act as RAM. However, Analysis & Synthesis cannot implement the registers as RAM hardware because a ramstyle synthesis attribute is set as "logic" for the registers.

ACTION: If you do not want Analysis & Synthesis to implement the register logic with RAM hardware, no action is required. If you want Analysis & Synthesis to implement the register logic with RAM hardware, remove the synthesis attribute or set a valid RAM attribute value.