ID:170125 The following nodes could not be optimally routed by the Fitter to improve DDIO timing

CAUSE: The Fitter detected DDIO_low registers in unexpected configurations. The Fitter may not be able to route these connections in the best way for DDIO timing.

ACTION: To obtain better DDIO timing, lock the DDIO cells to I/Os and adjoining Logic Array Blocks (LABs).