ID:170031 LE location constraint: <text> came from <text>

CAUSE: If a region constraint is listed, it came from one or more of the specified causes. This message is a submessage of the message that precedes it in the Messages window and in the Messages section of the Report window. Possible causes for location assignments include:

• You created location constraints with fixed locations.
• You assigned nodes and entities to a Logic Lock region. An LE may have no constraints but have a constraint source listed as a Logic Lock region. This happens if the fitter removes the Logic Lock due to conflicting user constraints. In this case a Warning message will be issued.
• Nodes and entities are connected to a signal that you placed on a dedicated clock routing network. The driver of the signal may be locked to a specific location that can drive that network.
• Nodes and entities are connected to a signal that the Auto Global Clock logic option placed on a dedicated clock routing network. The driver of the signal may be locked to a specific location that can drive that network.
• Nodes and entities are connected to a signal that is driven from a dedicated regional clock network. They are constrained to be in the area reachable by that network.
• Nodes and entities are connected to a signal that is driven from a dedicated fast regional clock network. They are constrained to be in the area reachable by that network.
• Nodes and entities were combined with other nodes and entities by the Auto Packed Registers logic option, and the resulting node or entity is constrained to a location that satisfies all of the location constraints on the original node or entities.
• Nodes and entities include a register which has been placed in an I/O register to improve circuit performance. The resulting I/O is constrained to a location that satisfies all of the location constraints on the original nodes and entities.
• Nodes and entities include a register which has been placed in an I/O register by the Fast Output Register or Fast Input Register option. The resulting I/O is constrained to a location that satisfies all of the location constraints on the original nodes and entities.
• Nodes and entities are embedded memory cells that have been placed into a single RAM, and it is constrained to a location that satisfies all of the location constraints on the original embedded memory cells.
• Nodes and entities are part of a DSP block. They are connected to other nodes and entities in that DSP block that have location constraints. The location constraints have been copied, with suitable adjustments, to these nodes and entities.
• Nodes and entities include part of a carry chain. Other nodes and entities in that carry chain have location constraints. The location constraints have been copied, with suitable adjustments, to these nodes and entities.
• Nodes and entities include part of a register cascade chain. Other nodes and entities in that chain have location constraints. The location constraints have been copied, with suitable adjustments, to these nodes and entities.
• A node or entity is a configuration block or a dedicated I/O that is connected to a configuration block. (RUBLOCK/CRCBLOCK)
• A node or entity is a PLL or a dedicated I/O that is connected to a PLL.
• A node or entity is a dedicated differential I/O pin.
• A node or entity is a GXB PLL or is connected to a GXB PLL.
• You created preferred locations for nodes or entities in a Logic Lock region. Preferred locations are used as a suggested initial placement for incremental placement and the Fitter may not enforce them.
• Nodes and entities were given preferred locations by Fitter netlist optimizations. Fitter netlist optimizations take advantage of placement information to optimize the netlist for Fm ax. It creates preferred location assignments on nodes and entities so that the optimized netlist can be placed using incremental placement.
• Nodes and entities include I/O cells that were placed while trying to obey restrictions on I/O banks.
• Nodes and entities are global/regional or fast regional clock I/O pins.
• A node or entity drives a global signal that can only be driven from this location.
• The node or entity is a DQS I/O or DQ I/O pin.
• The node or entity is used for JTAG boundary-scan testing.
• Nodes and entities include an inverter which has been implemented by a programmable inverter on the output of a DSP block. The resulting DSP block is constrained to a location that satisfies all of the location constraints on the original nodes and entities.