ID:13150 <name>
CAUSE: EMIF/PHYLite systems sharing a reference clock must use identical signals for clock and reset inputs.
ACTION: Connect the clock/reset inputs of the io_aux to identical signals.
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CAUSE: EMIF/PHYLite systems sharing a reference clock must use identical signals for clock and reset inputs.
ACTION: Connect the clock/reset inputs of the io_aux to identical signals.