ID:15550 Clock router will preserve the counter order because <text>

CAUSE: The counter order of the Quartus Prime Settings File (.qsf)) for the current PLL. Alternatively, it may be that the PLL is using dynamic reconfiguration (that is, the scanclk port is connected), or advanced PLL parameters are being used. This option forces the Quartus Prime software to use the PLL counters that correspond to the PLL clock outputs you specified. This condition may result in clock routing problems because the counters will not be rotated to resolve conflicts. This message is a submessage of the message that precedes it in the Messages window and in the Messages section of the Report window.

ACTION: No action is required. If this condition is not intended, turn off the PLL Preserve Counter Order logic option.