ID:130011 If the specified primitive is instantiated inside an Altera UNIPHY IP Core, make sure that top-level ports of the UNIPHY core are connected properly.

CAUSE: If the specified primitive is a DLL, DQS delay chain or other memory IP primitive that is instantiated inside an Altera UNIPHY IP core, make sure that all top-level ports of the UNIPHY core are connected properly. If you configured the UNIPHY core as a slave memory interface, make sure that all PLL and DLL input ports are driven by corresponding PLL and DLL output ports of the master UNIPHY IP Core.

ACTION: Correct the connectivity of the specified primitive, either directly, or by fixing connectivity of to the higher-level IP block. Additionally, if the UNIPHY IP core was generated in a previous version of the Intel FPGA Quartus Prime software, try to regenerate the UNIPHY core.