ID:130001 The <name> primitive is driven by the "<name>" output port of a <name> primitive "<name>". This configuration requires the PHYSICAL_CLOCK_SOURCE parameter of the "<name>" primitive to be "<number>"

CAUSE: Connecting the phasectrl input port of a CLK_PHASE_SELECT primitive to a specific DQS_CONFIG output port implies the use of a specific type of CLK_PHASE_SELECT multiplexer in the FPGA. To use this multiplexer, the LEVELING_DELAY_CHAIN primitive that drives the clkin input port of the CLK_PHASE_SELECT primitive must have the correct value for its physical_clock_source parameter.

ACTION: Check the configuration of the CLK_PHASE_SELECT primitive. The phasectrl input port may be connected to the wrong DQS_CONFIG output port, or the clkin port of the CLK_PHASE_SELECT primitive may need to be connected to a LEVELING_DELAY_CHAIN primitive with the correct value for the physical_clock_source parameter. See the sub-messages for the name of the DQS_CONFIG port that drives clkin input as well as the expected value of the physical_clock_source parameter of the LEVELING_DELAY_CHAIN primitive in this configuration.