ID:15575 None of the inputs fed by the compensated output clock of PLL "<name>" in Source Synchronous mode are set as the compensated input

CAUSE: The specified PLL is in Source Synchronous mode, but none of the inputs fed by the compensated output clock of this PLL are set as compensated input. The Quartus Prime software automatically sets those inputs as the compensated inputs.

ACTION: Either ignore this warning use the pll_compensate assignment to compensate the input by the PLL.