ID:11116 PLL output counters 0-3 or 14-17 are not used for driving the PHY clock tree in your device

CAUSE: PHY clock tree is driven by one or more high skew phase-locked loop (PLL) outputs.

ACTION: Use the set_location_assignment <PLL counter location> -to <PLL output signal> to constrain the PLL counters that drive the PHY clock tree.