ID:10621 VHDL Use Clause error at <location>: more than one Use Clause imports a declaration of simple name "<name>" -- none of the declarations are directly visible

CAUSE: In a VHDL Design File (.vhd) at the specified location, you used the specified simple name. However, Quartus Prime Integrated Synthesis cannot match the simple name to a unique declaration because more than one Use Clause in the current scope imports a declaration for the simple name. To avoid a naming conflict, none of the declarations for the simple name were made directly visible in the current scope. This message often occurs when the design imports the declarations in both the NUMERIC_STD and the STD_LOGIC_ARITH packages into the same scope; both packages declare types with the simple names UNSIGNED and SIGNED. This message also occurs when a design imports the declarations in both the STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED packages into the same scope; both packages define overloaded operators for STD_LOGIC_VECTOR arguments.

ACTION: Remove the naming conflict by eliminating all but one of the Use Clauses that declare objects with the specified simple name. You can also convert this reference to the simple name into a selected name that indicates the correct declarative scope.