ID:10656 VHDL Message Directive error at <location>: message directives cannot precede a design unit other than an entity or architecture

CAUSE: In a Verilog Design File (.v) or VHDL Design File (.vhd), you used a message directive before a VHDL design unit other than an entity or architecture. You can only specify message directives before entities and architectures.

ACTION: Remove the illegal message directive.