ID:10417 VHDL Association List error at <location>: unconstrained formal port "<name>" can only be associated in whole

CAUSE: In an Association List in a VHDL Design File (.vhd) at the specified location, you attempted to associate the subelements of the specified unconstrained formal port individually. Quartus Prime Integrated Synthesis does not support this functionality. When you declare a formal port with an unconstrained array type, you must associate a value with the entire port.

ACTION: Constrain the formal port, or only associate values with the entire port.