ID:10573 VHDL Component Instantiation Statement error at <location>: conversion function for formal parameter must contain only one argument

CAUSE: In a Component Instantiation Statement at the specified location in a VHDL Design File (.vhd), you specified a conversion function for a formal parameter of a component. However, you specified two or more arguments for the conversion function. The conversion function must contain only one argument; that is, you must pass only one argument to a conversion function.

ACTION: Change the conversion function so that it uses only one argument.