ID:10380 VHDL error at <location>: <type> type is used but not declared as an array type

CAUSE: In a VHDL Design File (.vhd) at the specified location, you used the specified type as if it were an array type. However, the type is not an array type. For example, the Signal Declaration in the following code specifies the range of (0 to 1) for the STD_LOGIC type, but the STD_LOGIC type is not an array type:

ENTITY example IS
   PORT ( ex1:  OUT  BIT );
END ENTITY;
 
               
ARCHITECTURE error_test OF example IS
   SIGNAL sig3: STD_LOGIC(0 to 1);
 
               
BEGIN
   ex1 <= '1';
END error_test;