ID:10585 VHDL Component Instantiation Statement error at <location>: argument for conversion function cannot contain a formal parameter

CAUSE: In a Component Instantiation Statement at the specified location in a VHDL Design File (.vhd), you specified a conversion function for a formal parameter of a component. However, you specified both a formal parameter and an actual parameter as the argument for the conversion function. The argument cannot contain a formal parameter. The argument must contain only an actual parameter; that is, you must pass only an actual parameter to a conversion function.

ACTION: Remove the formal parameter from the argument for the conversion function.