ID:10395 VHDL Conditional Signal Assignment error at <location>: conditional waveforms must have same number of elements

CAUSE: In a Conditional Signal Assignment at the specified location in a VHDL Design File (.vhd), you used more than one conditional waveform. However, the different conditional waveforms do not contain the same number of elements. For example, the Conditional Signal Assignment in the following code contains one conditional waveform with one element, and one conditional waveform with two elements.

ENTITY my_entity IS
   PORT
   (
      i: IN BIT
   );
END my_entity;
 
               
ARCHITECTURE a OF my_entity IS
   SIGNAL s1: bit_vector(1 downto 0);
BEGIN
   s1 <= "0" WHEN i = '1' ELSE 
         "11";
END a;

All the conditional waveforms in a Conditional Signal Assignment must have the same number of elements.