ID:10628 VHDL error at <location>: can't implement register for two clock edges combined with a binary operator

CAUSE: In an expression at the specified location in a VHDL Design File (.vhd), you attempted to combine two different clock edges with a binary operator. For example, in the following code, an expression combines clk1 and clk2 using the binary OR operator:

PROCESS (clk1, clk2)
BEGIN
    IF(rising_edge(clk1) OR rising_edge(clk2)) THEN
        q <= data;
    END IF;
END PROCESS;

               

            

This message can occur when you attempt to infer an edge-controlled register that is sensitive to two or more clock edges. However, the Quartus Prime cannot infer a register that is controlled by more than one clock.