ID:10647 VHDL type inferencing error at <location>: type of expression is ambiguous - "<type1>" or "<type2>" are two possible matches

CAUSE: In a VHDL Design File (.vhd) at the specified location, you used an expression that matched two or more types during type inferencing. As a result, Quartus Prime Integrated Synthesis could not uniquely resolve the type of the expression. For example, in the following VHDL code fragment, the expression a & b has ambiguous type because it could be either nibble_array or unsigned.

  subtype nibble is unsigned(3 downto 0);
  type nibble_array is array(natural range <>) of nibble;
  signal a, b  : nibble;
  signal tmp : signed(7 downto 0);
  
               
  tmp <= signed(a & b);