ID:10211 Verilog HDL unsupported feature error at <location>: recursive Task Enable Statement in Task Declarations is not supported

CAUSE: A Task Declaration in a Verilog Design File (.v) contains a recursive Task Enable Statement at the specified location. However, Quartus Prime Integrated Synthesis does not support recursive Task Enable Statements in Task Declarations.

ACTION: Rewrite the Task Declaration to remove the recursive Task Enable Statement.