ID:10248 Verilog HDL unsupported feature error at <location>: unsupported use of both Defparam Statement(s) and an ordered Module Instance Parameter Value Assignment list to specify parameter values for instance "<name>"

CAUSE: In a Verilog Design File (.v) at the specified location, you used both a Defparam Statement and an ordered Module Instance Parameter Value Assignment list to change the value of parameters in a module that you are instantiating. However, although Verilog-2001 supports the use of both a Defparam Statement and an ordered Module Instance Parameter Value Assignment list to change an instantiated module's parameter values, the Quartus Prime software does not support this use.

ACTION: Edit the design so that it uses either the Defparam Statement or the ordered Module Instance Parameter Value Assignment for the Module Instantiation. You may also convert the Module Instance Parameter Value Assignment list from an ordered list to a named list; the Quartus Prime software supports the use of both named Module Instance Parameter Value Assignment lists and Defparam Statements to specify parameter values for the same instantiated module.