ID:10206 Verilog HDL Module Declaration error at <location>: top module port "<name>" is not found in the port list

CAUSE: In a Verilog Design File (.v) at the specified location, you referenced the specified port name for the top-level module, but the specified port name is not found in the list of ports in the top-level module's Module Declaration.

ACTION: Edit the design to make sure the port name appears in the list of ports in top-level module's Module Declaration.