ID:10161 Verilog HDL error at <location>: object "<name>" is not declared. Verify the object name is correct. If the name is correct, declare the object.

CAUSE: In a Verilog Design File (.v) at the specified location, you referred to an object with the specified name. However, Quartus Integrated Synthesis was unable to match the name to an object whose declaration is visible in the current scope.

ACTION: Verify that the object name is correct, for example, that the object name is spelled correctly. If the name is correct, declare the object.