ID:10183 Verilog HDL Module Instantiation error at <location>: too many parameter values (<number>) for instance of module "<name>", which declares <number> formal parameter(s)

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you specified parameter values for a module instance. However, the number of parameter values exceeds the number of formal parameters declared by the module.

ACTION: Specify fewer parameter values for the module instance, or declare more formal parameters for the module.