ID:10214 Verilog HDL Module Instantiation error at <location>: module "<text>" expects fewer than <number> parameters

CAUSE: In a Module Instantiation at the specified location in a Verilog Design File (.v), you used an ordered parameter assignment list to assign values to the instantiated module's parameters. However, the ordered parameter assignment list contains more parameters than are declared in the Module Declaration.

ACTION: Make sure the number of parameters in the ordered parameter assignment list is the same as the number of parameters declared for the module in the Module Declaration. If necessary, remove parameters from the ordered parameter value list or add parameters to the Module Declaration's module_parameter_port_list.