ID:10095 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: incorrect output field length in UDP table "<name>"

CAUSE: In a user-defined primitive (UDP) declaration at the specified location in Verilog Design File (.v), you entered an incorrect output field length in a UDP table. A UDP table can have only a single 1-bit output signal.

ACTION: Correct the table output so it has only a single 1-bit output signal.