ID:10177 Verilog HDL syntax error at <location>: table entry is missing colon ':' I/O separator

CAUSE: In a user-defined primitive (UDP) definition at the specified location in a Verilog Design File (.v), one of the lines of the UDP table definition is missing the colon character (:) that separates inputs from outputs.

ACTION: Insert a colon (:) between the inputs and outputs in the table.