ID:10171 Verilog HDL syntax error at <location> near end of file <text>

CAUSE: In a Verilog Design File (.v), a syntax error occurred near the end of the file at the specified location. For example, this error may occur if required punctuation, such as a semicolon or parenthesis, is missing at the end of the file.

ACTION: Check for and fix syntax errors at the end of the file. The error message will report possible expected syntactical elements.