ID:10184 Verilog HDL User-Defined Primitive (UDP) Declaration error at <location>: the first UDP port must be an output

CAUSE: In a user-defined primitive (UDP) declaration at the specified location in a Verilog Design File (.v), you did not specify or declare an output as the first port in the port list. A UDP must have a single output port, and the output port must be listed first in the port list.

ACTION: Specify or declare an output port as the first entry in the UDP port list.