ID:10284 Verilog HDL Module Instantiation error at <location>: port "<name>" is not declared by module "<name>"

CAUSE: In a Verilog Design File (.v), you instantiated a module and connected to a port of the module with the specified name. However, the declaration of the module you instantiated does not declare a port with the specified name.

ACTION: Check the declaration of the module instantiation for declared port names.