ID:10135 Verilog HDL Module Declaration error at <location>: explicit port identifier "<name>" cannot be used more than once

CAUSE: In a module declaration at the specified location in a Verilog Design File (.v), you attempted to create an explicit (named) port using the specified port identifier. However, you have already used the specified port identifier to declare another explicit port in the module's list of ports. All explicit port identifiers must be unique.

ACTION: Assign a unique name to each explicit port.