ID:10111 Verilog HDL Module Instantiation error at <location>: cannot override parameters -- module "<name>" does not expect any parameters

CAUSE: In a Verilog HDL Module Instantiation at the specified location in a Verilog Design File (.v), you specified a Module Instance Parameter Value Assignment to override one or more specified parameters for the instance; however, no parameters have been defined for the module.

ACTION: Edit the Module Declaration to define parameters or remove the parameter overrides that are specified in the Module Instance Parameter Value Assignment.