ID:10954 Verilog HDL Generate error at <location>: loop condition must be a constant expression

CAUSE: In a generate loop at the specified location in a Verilog Design File (.v), you used a loop condition that does not evaluate to a constant true or false during elaboration. Verilog HDL requires generate loop conditions to be a constant expression.

ACTION: Remove from the loop condition any references to non-constant objects such as variables and nets.