ID:10239 Verilog HDL Always Construct error at <location>: event control cannot test for both positive and negative edges of variable "<name>"

CAUSE: In an always construct at the specified location in a Verilog Design File (.v), you used an event control to test for both the positive and negative edges of the specified variable, possibly in an attempt to infer positive and negative edge-triggered registers in the same construct. For example, in the following code, the always construct's event control tests for multiple edges of clk:

               
reg q_pos, q_neg;
 
               
always @ (posedge clk or negedge clk) begin
   if (clk == 1'b1)
      q_pos <= data;
   else
      q_neg <= data;
end

            

Quartus Prime Integrated Synthesis cannot infer both types of registers in the same construct, nor can it infer dual-edge triggered registers.

ACTION: Change the event control so it tests for a signal edge. If you want to infer both negative and positive edge-triggered registers, factor the always construct into two separate always constructs with different event controls.For the previous example, you can use one always construct for the posedge test and another always construct for the negedge test:

reg q_pos, q_neg;
 
               
always @ (posedge clk) begin
   q_pos <= data;
end
always @ (negedge clk) begin
   q_neg <= data;
end