ID:10220 Verilog HDL error at <location>: ports in module "<text>" cannot be declared using both a formal port declaration list and internal port declarations

CAUSE: In a Module Declaration at the specified location in a Verilog Design File (.v), you used both a formal port declaration list (where the Module Declaration port list contains only port names, and the Module Declaration body contains the Port Declarations) and internal port declarations (where the Module Declaration port list contains the Port Declarations, and the Module Declaration body contains no Port Declarations). However, you can use only one of these styles to declare the module's ports.

ACTION: Use either a formal port declaration list or internal port declarations to declare a module's ports.